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clock divider circuit

Master Clock and Divider Circuit.

Using the 74HC163 Counter as a clock divider, the master 14.318 MHz clock is fed in, and the Q0 output is used to divide by two for a 7.159 MHz output clock. The original 14.318 MHz clock is also tapped so that it can be routed to the Video Generator section for later use. I may use the Q3 tap later as well to send an 895 KHz clock (divide by 16) out to the Sound Generator for later division.

cock waveforms

Testing the Master Clock and it divisor.

Probing the Master Clock and the divide by two clock, I get the expected 14.318 MHz and 7.159 MHz clocks, which are in sync with each other. The ugly round corners of the square pulses are due to the fact that I just jammed a piece of wire into the breadboard and fed it to my scope with zero consideration for termination and capacitance. It’s close enough to see that the circuit is functioning.

nand gate connected to rw and ph2

Qualifying RW with PH2 on the 6502.

For those who are familiar with the operation of a 6502 microprocessor, then you know that you have to “qualify” the read and writes to memory with the input clock on the 6502’s Phase 2 clock input pin. What this means is that the 6502 is only allowed to read or write to its SRAM when the clock that drives it is in the high state. To achieve this criteria, the clock is gated with the RW pin so that the SRAM is in the idle state (WE and OE high) whenever the 6502’s clock (PH2 Pin) is low. A single NAND gate can be used to make this circuit, as shown here, with the schematic below.

RW and PH3 qualifying circuit

The 6502 Clock is gated with RW through the NAND Gate.

The circuit shown above only allows the 6502 access to the SRAM during the high phase of the clock feeding its PH2 clock input pin. With PH2 and RW both high, the 6502 is safe to read whatever data is presented on the data bus by the SRAM. With PH2 high and RW low, the SRAM will accept the data and address given at the time, and write that data into memory.

Following the path through the two NAND gates used, the 6502 RW signal is inverted then fed forward directly to the Output Enable on the SRAM. This inverted signal is fed into one input on the other NAND gate, which has its other input driven by the clock signal. The output of this NAND gate is then fed to the Write Enable of the SRAM. This circuit meets the logic shown in the included truth table, and is about as simple as can be made with 7400 logic, passing through 2 gates for an 10-16 nanosecond propagation delay.

74HC574 latch controle line

Control Lines to Latch Addresses.

The load the SRAMs with the 6502 Operating System (VOS) on startup, the 6502 is held in reset and tristated on the bus while the AVR dumps the ROM to the SRAM. Because a single 8 Bit path is used, latches (74HC574) are required to latch both the address and data for initialization. The Boot Loader is basically a sequencer that latches each 8 bit segment of data as it dumps it as; Address LO, Address HI, and Data.

So to fill the entire 64K of SRAM, the sequencer has to send 196,608 latched bytes of data, 2 of which are addresses, followed by the data to be stored to the SRAM. The Boot Loader is just a ROM dumping counter that does what it has to do once and then hides from the bus once the 6502 takes over.

6502 Address Bus

Adding the 6502 Address Bus wiring.

Now that The Boot Loader has the ability to latch the required address and data bytes on startup, the final wiring to complete will be the Address Lines. Unlike the Data Bus, which is connected to all IC that use it, the Address Bus is only available to the 6502 and it’s dedicated 64K SRAM. The Boot Loader can only drive the Address Bus on startup by latching out 2 bytes to create the 16 bit address, and it can only do this while the 6502 is held in reset and off the bus.

This photo shows the 6502 directly connected to the SRAM with its 8 Bit Data Bus (Blue) and 16 Bit Address Bus (white). I will be using white wires for all Address Bus wiring so it is easy to identify. Now the two Address Bus latches need to be connected so that I can test boot the 6502.

Single byte output test

A Data Latch controlled by a Comparator.

Now that the “Hello World” milestone has been met, it is time to test the IO system in much more depth, decoding individual addresses and also testing input as well as output. It is great to be at this point in the project now, and it won’t be long before the Video System gets built, giving Vulcan-74 a screen to say “Hello World” in full color.

To test the rest of the IO system, several of the 74HC138 demultiplexers have to be connected so that addressing can happen at the fine grain level. Vulcan-74 is capable of addressing 256 individual 8 Bit IO locations, so it could control 2048 individual LEDs, but that is not the goal. I will probably need “only” 128 of the 8 bit locations to control all functions on the board, but I won’t really know for sure until the design progresses. I do have a tentative list, and the sound generator alone will use at least 64 of the 128 possible address locations. For now, more basic testing has to be done.

32 LED chaser

32 LEDs Addressed as 4 Bytes. One on at a time.

To completely test the IO output functionality, it was necessary to add a few of the 74HC138 demultiplexers into the mix in order to ensure that latching would occur at the correct time. Because the 6502 expects the circuit to latch output data on the high phase of the system clock (PH2) and on the low phase of R/W, it is important to keep propagation delay to a minimum so that setup and hold times are met.

This photo shows the LED Chaser program working perfectly, addressing 32 individual LEDs as blocks of 8 LEDs per byte. As per the circuit below, the entire IO decoding system will be capable of addressing 128 bytes, but only 4 of the 128 bytes are used to chase the 32 LEDs. The video demonstrates the LED Chaser program in action, as well as the Boot Loader getting the 6502 up and running.

IO decoder schematic

Address Decoder section with 128 IO locations.
Click here for a larger PDF version.

The Address Decoder is mainly made of 74HC138 demultiplexers, or 3-8 Line Decoders as they are also called since they take a 3 bit binary address and select one of 8 possible outputs. Since only one of the 8 outputs is low at any one time, these demultiplexers are perfect for this use as they can drive either a 74HC574 latch or a 74HC245 buffer directly. To latch output data, as we require in the 32 LED chaser, the decoder output is connected to the latch clock so that any transition stores the data in the latch. This makes each latch a one byte write only RAM.

To read data, the decoders output will be connected to the output enable line of a 74HC245 buffer or 74HC574 latch so that the output is fed into the 6502 bus only when requested by the 6502 at that specific address. In this application, the 245 or 574 acts as a one byte read only ROM.

4 byte 32 LED latching circuit

BattleStar Galactica style LED Chaser!

The LED Chaser program shown below is a very basic test that accomplishes several things such as testing the boot system, 64K program memory, clock divider, qualification circuit, and the IO system. There were so many things that could have went wrong here, so I was surprised to see the LEDs moving back and forth as soon as I switched on the power. I certainly have more luck with 1970’s tech than I do with any modern tech!

The code that is running the LED Chaser was complied with a PC program called “6502 Macro Assembler”, written by Michal Kowalski and is available here…

I exported the 64K binary image into the AVR that loads up the 64K Program Memory once on power up, and this is what the 6502 runs once it is out of reset.

The LED Chaser reminded me of the Cylon Raiders from the 1978 TV series BattleStar Galactica, which is one year older than the original 6502! Most likely, they made their LED chaser using 74LS4017 decade counters and a 555 timer to run them, since no affordable and easy to use CPU was yet available.

The next IO test to be done will be a read test, which is similar to this test, but with the output of a 74HC245 sending data to the bus rather than recording it like the 75HC574s were doing. I will connect the 245 buffers input to a 9 pin Commodore / Atari compatible joystick for testing and then display the output on the LEDs since they are already in place and acting as my primary display system.

More to Come Soon!

I work on this project on spare weekends when my homesteading chores are done for the day. This blog will grow to hundreds of photos before the end, and Vulcan-74 will evolve and adapt until it is the exact machine I dreamed of creating way back in 1980!

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Vulcan-74 Build Log

I plan on adding to the project at least once per week.

Long live 6502!
– Radical Brad

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