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IC body close-up

Shaved ICs making efficient use of space.

The modified body ICs now look the same as my other ICs that don’t waste breadboard space.  There is even enough room between the packages to sneak a few wires if I need to cross from one breadboard panel to the next. For this project, I have modified 32 new 74HC245 buffers ahead of time, as I use these a lot. The other IC I use a lot of is the 74HC574 data latch, but luckily these ones alreay fit together nicely, so they don’t need to be hacked.

Ready to build a retro computer!

The possibilities are endless!

This shall be the beginning of Vulcan-74. I have a massive empty breadboard with all of its power rails wired, as well as the IO ports I intend to use. Next to the MOAB (Mother Of All Breadboards) sits my Commodore 1702 monitor, ready to display all of the magic that is soon to come from hundreds of 1970’s logic gates and a 6502 CPU.

On top of my Commodore monitor is a 300 page printed manual on 6502 architecture and assembly language, most of which I know by memory now as if it was a second language.

These are the good ole’ days!

3 generations of 6502 cpus

Several generations of 6502 CPUs.

In an earlier post, I mentioned that I am using CMOS variant logic on this project, which is a much more power friendly version of the original TTL based logic. The operation and pinouts on all of the 7400 based logic chips and the 6502 are exactly the same, but I will be able to use a much smaller power supply with CMOS based logic. I will probably run the entire board (500+ ICs) from a small 2 amp wall wart, but if I was using TTL logic, the power supply would be massive, perhaps 80 amps or more! That would be a car battery worth of power, running at its full current draw! Yikes.

Shown in this photo are several generations of 6502s I have in my collection. The top 6502 is and original 1975 dated ceramic body IC with gold pins, and it still works just fine if I drop it into my Commodore PET or VIC-20. The center 6502 is the common mass produced plastic body IC used in all of the home computer greats of the late 1970’s through to the end of the 1980’s. Both of these 6502 units are of the TTL variant, so they would not work well in my 74HC (CMOS) design without a level translator.

The bottom 6502 is a modern Western Design Center produced IC that is still available today, and is CMOS compatible for modern use. The modern 6502 is almost exactly the same as the 40 year old original, and will run all of the code made for the original. The new 6502 does have a few extra OP Codes, and a function to allow the bus to tristate, but other than that it is the same 6502 inside.

Vulcan-74 basic schematic

Schematic for the 6502 Boot Loader and IO System.
Click here for a larger PDF version.

Vulcan-74 will be designed in several stages, based on sections of circuitry that define a larger function. Since one section controls the next, it only makes sense to start with the sections that can be tested as they are built on the breadboard. The 6502 controls everything, so it must be able to boot and talk to the low level logic before I can move on to larger sections of the board such as the Video Generator, Sprite Generator, Sound Generator, and Storage System.

Normally I don’t do schematics! Yeah, really, I just pencil down some basic ideas in flow chart form, and then start adding chips and wires. I have been doing this for so long that it just seems natural, just like typing this blog, but this time I am going to document everything. Moving forward, I am starting with schematics that are going to be a very close and accurate representation of the circuit that I intend to build and test. Schematics will be updated when necessary to represent the actual circuits on the MOAB.

This small section of Vulcan-74 does two 6502 specific functions; it loads the Operating System code into the 6502 memory, and it decodes 256 individual IO lines mapped from address 512 to address 767. The reason I placed my decoded IO lines at address 512 is because the 6502 uses addresses from 0 to 255 as Zero Page (single addressable faster RAM), and addresses from 256 to 511 for its Stack Functions. I chose the next available segment of memory for hardware IO, which starts at address 512.

layout of 6502 cpu side

Collecting ICs for the 6502 section of the board.

I printed out the large schematic on several sheets of paper and then taped them together so I could see it easily and have room to make revisions, which will certainly be plentiful indeed. The printed schematic was so large that I could actually place the ICs on the paper as I collected them from my parts bins.

This part of the board will use somewhere around 25 ICs, so it may only utilize 5 of the 48 breadboard panels I have to work with. That should be ok, but I still believe that the final board may require a bit more real-estate by the time I am done. The Sound Generator alone may require more than one half of the MOAB, so I may have to prototype only two of the four audio channels for testing.

layout of rom loader side

Vulcan-74 will be a no-ROM 6502 system.

A 6502 based computer system can access a total of 64K at one time, and most designs include some amount of RAM and ROM, with RAM being used for working variables, and ROM being used to store the boot program or general operating system. Vulcan-74 breaks from this standard design, and uses only RAM so that the compiled program can utilize the entire 64K when it is loaded. The OS is initially boot loaded into the 64K SRAM by an AVR acting as ROM. I did this so I would not have to invest in an ancient ROM burner and waste time burning ROMs for each code change.

I will be including a feature rich operating system as well that includes a built in 6502 code editor as well as an assembler and several utilities, and it will probably require the entire 64K when complete. In order to allow editing of massive 6502 programs (including text comments), the OS will actually leverage one Megabyte of extra memory, latched in and out through some of the IO hardware. You can see this “Program Memory” shown above in the form of the two hand wired 512K SRAMs mounted to the sockets. Now the OS can show the program listing stored in the large Program Memory while utilizing its entire 64K of 6502 accessible memory to run the OS and related tools.

I chose one megabyte for the Program Memory based on the maximum possible source code size of a full 64K program, including instructions and text comment with formatting. Based on a 40 column display and the fact that 6502 instructions average 2.5 bytes for storage, the maximum number of code lines would be about 26,000 lines of 40 column text. Assuming a few extra hidden characters (4 bytes) for color formatting per line, this equates to 44 * 26000 = 1,144,00 bytes, which is very close to one megabyte. In reality, comments and spaces will account for a lot of the code text, so there should be more than enough room for a massive 64K 6502 program to be loaded and edited.

placement of breadboard components

Test fitting the first few ICs on the MOAB.

On a board of this size, it is important to consider the path of high speed signals, busses, as well as the distance between them. Even though the wires and ICs just pop out, moving large segments of a breadboard is a tedious task at this scale. I also trim all wires to the minimum length and shape them around ICs when a section of the circuit works well, so a large reshuffling of ICs also means redoing custom length wires.

Another consideration here is the fact that the IO ports are placed at the top of the board, so relevant sections like the Video Generator and Controller Port should be placed closer to their respective ports at the top of the board. In the photo shown here, the left half of the board is everything required to boot the 6502 as well as the latching to access the extended one megabyte of Program Text Memory. The right side of the board is all 74HC138 (4-8 decoders) ICs that will be used to decode the 256 possible IO lines.

I installed only 14 of the 74HC138’s at this point as I have no idea how many IO lines I actually need. With that many 138’s, I can decode up to 96 IO, but only plan on wiring enough for 64 IO lines initially. 64 IO lines may be plenty for all of the hardware functions of the completed system, but I will leave space on the second board for more decoding just in case. The IO decoding is placed at the very bottom of each board so I can work upwards, placing output generating functions closer to the ports at the top of the boards.

6502 system with romless kickstart

This is the 6502 Loader and Program Memory.

These 12 ICs form a complete working 6502 computer system with 64K of memory to execute programs, and one megabyte of extended memory to hold program source code text. The 5 ICs across the top are 74HC574 data latches, which are used to latch the 20 bit address bus to the dual 512K Program Memory SRAMs, and the 16 bit address bus to the 6502’s standard 64K of SRAM. Latching is required since the 6502 only has a 16 bit address but available for accessing memory.

The large IC on the bottom left is an AVR that holds the 6502 Operating System binary code. The AVR pretends to be ROM, and is clocked out to the 64K 6502 SRAM once on power up. Once the 6502 boots, the AVR tristates and simply disappears from the entire system like a ghost. This is my solution to finicky ROM burners and hard to find ICs.

The smaller IC sitting between the 6502 on the right and its 64K SRAM on the left is a 74HC00 NAND gate that qualifies the 6502 clock with memory access to ensure data integrity and timing. This part of the circuit is straight out of the 6502 manual and shown in almost every 6502 system ever made. I also make use of one of the free NAND gates in this IC to drive a comparator later on.

The final IC on the far lower right is a 74HC688 data comparator, which is used to detect equality between two different 8 bit values. In this case, one value is tied to “2” and the other value directly to the high address bus of the 6502. This means that the comparator is triggered any time the 6502 address bus is set to any value between 512 and 767. The reason for this is because 2*256=512, so only the second bit of the high address bus will trigger an output on the comparator. The low address bus is passed along to the 74HC138’s, which then decode one of the 256 possible values as a hardware IO line.

This section of Vulcan-74 will now be built and tested, with the goal being the boot load of a 6502 program into the 64K RAM and then an IO toggling of at least 64 of the IO lines. Once that functionality is present, the 6502 will have hardware control of everything else I build, and I will be able to quickly write 6502 assembly and load it directly into the bootloader for testing.

512K SRAMs and DIP sockets

DIP sockets and 512K SRAMs in SOJ packages

I know that Vulcan-74 will require massive SRAM requirement to handle multiple layers of video screens as well as sprites and sound samples. Now when I say massive, I don’t mean by today’s standards where a PC with 32 gigabytes of RAM is required just to boot windows and load all of Adobe Acrobat’s spyware in the background, what I am comparing to is computer RAM of the 1980’s era.

In 1980, 64K was a big deal on a home computer like a VIC-20, PET, or Apple II. In fact, most of those computers shipped new with half of that or less, leaving the user to add costly RAM to the system. Static RAM (SRAM), the most common type of memory of the era was very expensive and only available in small sizes such as 1K by 4 bits or 2K by 8 bits. Vulcan-74 as a comparison, will probably use more than 16 Megabytes of SRAM by the time it is done! That is more than 430 times the amount of free memory a Commodore 64 had available to the user!

SRAM is still available in DIP packages, but in searching, I found only 32K density, or expensive 512K density ICs in breadboard ready DIP format. The following series of photos will detail what I did to create 16 Megabytes of breadboard ready SRAM from commonly available 512K SRAMs.

SRAM is a SOJ package

40 Pin DIP Sockets to carry the SOJ SRAMs.

These SOJ (Small Outline J-Lead) packages have been readily available and affordable for a long time, and are still currently manufactured for many densities of of SRAM from 32K to 512K. The SOJ pin size is also large enough to be easily hand soldered, so I decided to mount them to 40 pin DIP sockets for breadboard use.

The socket shown here is a standard wide 40 pin DIP socket with solid round pins instead of thin flat legs. This style of socket is very robust, and can be easily pressed into a breadboard without worry of bending the pins. The top of the pins are hollow as well, so they are great for soldering wires onto, which is what I plan to do.

I have been asked why I don’t just make a pile of carrier PCBs for these or purchase pre made adapter boards from some ebay seller. Well the simply answer is that DIY is king, and that’s how I roll!

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